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High Performance, 145 MHz FastFETTM Op Amps AD8065/AD8066
FEATURES
FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, -3 dB bandwidth (G = +1) 180 V/s slew rate (G = +2) Low noise 7 nV/Hz (f = 10 kHz) 0.6 fA/Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV max High common-mode rejection ratio: -100 dB Excellent distortion specifications SFDR -88 dB @ 1 MHz Low power: 6.4 mA/amplifier typical supply current No phase reversal Small packaging: SOIC-8, SOT-23-5, and MSOP
APPLICATIONS
Instrumentation Photodiode preamps Filters A/D drivers Level shifting Buffering
CONNECTION DIAGRAMS
VOUT 1 -VS 2 +IN 3
4
AD8065
5
+VS
NC 1 -IN 2
AD8065
8 7 6
NC +VS VOUT
TOP VIEW (Not to Scale)
-IN
+IN 3 -VS 4
TOP VIEW 5 NC (Not to Scale)
AD8066
VOUT1 1 -IN1 2 +IN1 3 -VS 4 TOP VIEW (Not to Scale)
8 7 6 5
+VS VOUT2 -IN2 +IN2
02916-E-001
Figure 1.
GENERAL DESCRIPTION
The AD8065/AD80661 FastFET amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use. The AD8065 is a single amplifier, and the AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. proprietary XFCB process and allow exceptionally low noise operation (7.0 nV/Hz and 0.6 fA/Hz) as well as very high input impedance. With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and a bandwidth of 145 MHz, the AD8065/AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs. Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/s, excellent distortion (SFDR of -88 dB @ 1 MHz), extremely high common-mode rejection of -100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065/AD8066
1
operate using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current. The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP-8, and SOT-23-5. They are rated to work over the industrial temperature range of -40C to +85C.
24 21 18 15
GAIN (dB)
G = +10 VO = 200mV p-p G = +5
12 9 G = +2 6 3 G = +1 0 -3
02916-E-002
-6 0.1
1
10 FREQUENCY (MHz)
100
1000
Figure 2. Small Signal Frequency Response
Protected by U. S. Patent No. 6,262,633.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD8065/AD8066 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Maximum Power Dissipation ..................................................... 7 Output Short Circuit .................................................................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 15 Theory of Operation ...................................................................... 18 Closed-Loop Frequency Response........................................... 18 Noninverting Closed-Loop Frequency Response .................. 18 Inverting Closed-Loop Frequency Response ......................... 18 Wideband Operation ................................................................. 19 Input Protection.......................................................................... 19 Thermal Considerations............................................................ 20 Input and Output Overload Behavior...................................... 20 Layout, Grounding, and Bypassing Considerations................... 21 Power Supply Bypassing ............................................................ 21 Grounding ................................................................................... 21 Leakage Currents........................................................................ 22 Input Capacitance....................................................................... 22 Output Capacitance ................................................................... 22 Input-to-Output Coupling ........................................................ 23 Wideband Photodiode Preamp ................................................ 23 High Speed JFET Input Instrumentation Amplifier.............. 24 Video Buffer ................................................................................ 24 Outline Dimensions ....................................................................... 25 Ordering Guide........................................................................... 26
REVISION HISTORY
2/04--Data Sheet Changed from Rev. D to Rev. E. Updated Format.................................................................Universal Updated Figure 56 ......................................................................... 21 Updated Outline Dimensions...................................................... 25 Updated Ordering Guide.............................................................. 26 11/03--Data Sheet changed from Rev. C to Rev. D. Changes to Features ........................................................................ 1 Changes to Connection Diagrams ................................................ 1 Updated Ordering Guide................................................................ 5 Updated Outline Dimensions...................................................... 22 4/03--Data Sheet changed from Rev. B to Rev. C. Added SOIC-8 (R) for the AD8065............................................... 4 2/03--Data Sheet changed from Rev. A to Rev. B. Changes to Absolute Maximum Ratings ...................................... 4 Changes to Test Circuit 10 ........................................................... 14 Changes to Test Circuit 11 ........................................................... 15 Changes to Noninverting Closed-Loop Frequency Response 16 Changes to Inverting Closed-Loop Frequency Response ....... 16 Updated Figure 6 .......................................................................... 18 Changes to Figure 7....................................................................... 19 Changes to Figures 10 ................................................................... 21 Changes to Figure 11..................................................................... 22 Changes to High Speed JFET Instrumentation Amplifier....... 22 Changes to Video Buffer............................................................... 22 8/02--Data Sheet changed from Rev. 0 to Rev. A. Added AD8066 ..................................................................Universal Added SOIC-8 (R) and MSOP-8 (RM) ........................................ 1 Edits to General Description ......................................................... 1 Edits to Specifications ..................................................................... 2 New Figure 2 .................................................................................... 5 Changes to Ordering Guide ........................................................... 5 Edits to TPCs 18, 25, and 28........................................................... 8 New TPC 36 ................................................................................... 11 Added Test Circuits 10 and 11..................................................... 14 MSOP (RM-8) added.................................................................... 23
Rev. E | Page 2 of 28
AD8065/AD8066 SPECIFICATIONS
@ TA = 25C, VS = 5 V, RL = 1 k, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -5.5 V to +5.5 V G = -1, -5.5 V to +5.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 8 V Step fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 8 V p-p fC = 10 MHz, RL = 100 f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 VCM = 0 V, SOIC Package SOIC Package TMIN to TMAX TMIN to TMAX VO = 3 V, RL = 1 k Min 100 100 Typ 145 120 50 42 7 175 170 180 55 205 -88 -67 -73 24 7 0.6 0.02 0.02 0.4 1 2 25 1 1 113 1000 || 2.1 1000 || 4.5 -5 to +1.7 See the Theory of Operation section VCM = -1 V to +1 V VCM = -1 V to +1 V (SOT-23) RL = 1 k RL = 150 VO = 9 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 5 PSRR -85 6.4 -100 -85 -82 -4.88 to +4.90 -5.0 to +2.4 -5.0 to +5.0 -100 -91 -4.94 to +4.95 -4.8 to +4.7 35 90 20 24 7.2 1.5 17 6 10 Max Unit MHz MHz MHz MHz MHz ns ns V/s ns ns dBc dBc dBc dBm nV/Hz fA/Hz % Degree mV V/C pA pA pA pA dB G || pF G || pF V V dB dB V V mA mA pF V mA dB
Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR
130
Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio
100
Rev. E | Page 3 of 28
AD8065/AD8066
@ TA = 25C, VS = 12 V, RL = 1 k, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -12.5 V to +12.5 V G = -1, -12.5 V to +12.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 10 V Step fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 1 MHz, G = +2, VO = 10 V p-p fC = 10 MHz, RL = 100 f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 VCM = 0 V, SOIC Package SOIC Package TMIN to TMAX TMIN to TMAX VO = 10 V, RL = 1 k Min 100 100 Typ 145 115 50 40 7 175 170 180 55 250 -100 -67 -85 24 7 1 0.04 0.03 0.4 1 3 25 2 2 114 1000 || 2.1 1000 || 4.5 -12 to +8.5 See the Theory of Operation section VCM = -1 V to +1 V VCM = -1 V to +1 V (SOT-23) RL = 1 k RL = 350 VO = 22 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 5 PSRR -84 6.6 -93 -85 -82 -11.8 to +11.8 -12.0 to +9.5 -12.0 to +12.0 -100 -91 -11.9 to +11.9 -11.25 to +11.5 30 120 25 24 7.4 1.5 17 7 10 Max Unit MHz MHz MHz MHz MHz MHz ns ns V/s ns ns dBc dBc dBc dBm nV/Hz fA/Hz % Degree mV V/C pA pA pA pA dB G || pF G || pF V V dB dB V V mA mA pF V mA dB
Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Output Overdrive Recovery Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR
130
Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio
103
Rev. E | Page 4 of 28
AD8065/AD8066
@ TA = 25C, VS = 5 V, RL = 1 k, unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -0.5 V to +5.5 V G = -1, -0.5 V to +5.5 V G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 10 MHz, RL = 100 f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 VCM = 1.0 V, SOIC Package SOIC Package TMIN to TMAX TMIN to TMAX VO = 1 V to 4 V (AD8065) VO = 1 V to 4 V (AD8066) Min 125 110 Typ 155 130 50 43 6 175 170 160 60 -65 -50 22 7 0.6 0.13 0.16 0.4 1 1 25 1 1 113 103 1000 || 2.1 1000 || 4.5 0 to 1.7 See the Theory of Operation section VCM = 1 V to 4 V VCM = 1 V to 2 V (SOT-23) RL = 1 k RL = 150 VO = 4 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 5 5.8 -78 -74 -78 0.1 to 4.85 0 to 2.4 0 to 5.0 -100 -91 0.03 to 4.95 0.07 to 4.83 35 75 5 24 7.0 1.5 17 5 5 Max Unit MHz MHz MHz MHz MHz ns ns V/s ns dBc dBc dBm nV/Hz fA/Hz % Degree mV V/C pA pA pA pA dB dB G || pF G || pF V V dB dB V V mA mA pF V mA dB
Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third-Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio
105
100 90
PSRR
6.4 -100
Rev. E | Page 5 of 28
AD8065/AD8066 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering, 10 sec) Rating 26.4 V See Figure 3 VEE - 0.5 V to VCC + 0.5 V 1.8 V -65C to +125C -40C to +85C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. E | Page 6 of 28
AD8065/AD8066
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/AD8066. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), ambient temperature (TA), and total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as
2.0
MAXIMUM POWER DISSIPATION (W)
1.5 MSOP-8 SOIC-8 1.0 SOT-23-5
0.5
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
TJ = TA + (PD x JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package.
Airflow will increase heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC (125C/W), SOT-23 (180C/W), and MSOP (150C/W) packages on a JEDEC standard 4-layer board. JA values are approximations.
PD = Quiescent Power + (Total Drive Power - Load Power )
V V V OUT 2 PD = (VS x I S ) + S x OUT - RL RL 2
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure.
RMS output voltages should be considered. If RL is referenced to VS-, as in single-supply operation, then the total drive power is VS x IOUT. If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS x I S ) +
(VS /4)2
RL
In single-supply operation with RL referenced to VS-, worst case is VOUT = VS/2.
Rev. E | Page 7 of 28
02916-E-003
0 -60
AD8065/AD8066 TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: 5 V, CL = 5 pF, RL = 1 k, VOUT = 2 V p-p, Temperature = 25C.
24 21 18 15
GAIN (dB)
6.9 RL = 150 G = +10 VO = 200mV p-p 6.7 G = +5
GAIN (dB)
6.8
G = +2
VOUT = 0.2V p-p VOUT = 0.7V p-p VOUT = 1.4V p-p
6.6 6.5 6.4 6.3 6.2
12 9 G = +2 6 3 G = +1 0 -3
02916-E-004
6.1 6.0
02916-E-007 02916-E-009 02916-E-008
-6 0.1
1
10 FREQUENCY (MHz)
100
1000
5.9 0.1
1
10 FREQUENCY (MHz)
100
Figure 4. Small Signal Frequency Response for Various Gains
6 VO = 200mV p-p G = +1 4 VS = +5V 2
GAIN (dB) GAIN (dB)
Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)
9 VO = 200mV p-p G = +2 8 VS = +5V VS = 5V
7 VS = 5V
0 VS = 12V -2
6 VS = 12V 5
-4
4
02916-E-005
-6 0.1
1
10 FREQUENCY (MHz)
100
1000
3 0.1
1
10 FREQUENCY (MHz)
100
1000
Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42)
2 VO = 2V p-p 1 0 VS = 5V
GAIN (dB)
Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43)
8 7 6 VS = 12V
GAIN (dB)
G = +1
G = +2
VS = +5V
VS = 5V
-1 VS = 12V
5 4 3
-2
-3 2 -4 1
02916-E-006
-5 0.1
1
10 FREQUENCY (MHz)
100
1000
0 0.1
1
10 FREQUENCY (MHz)
100
1000
Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42)
Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43)
Rev. E | Page 8 of 28
AD8065/AD8066
9 VO = 200mV p-p G = +1 6 CL = 25pF CL = 20pF
GAIN (dB)
8 CL = 25pF RSNUB = 20 6 CL = 5pF 4 CL = 55pF CL = 25pF 2 0 -2 -4
3
GAIN (dB)
0 CL = 5pF -3
-6 -6
02916-E-010
VO = 200mV p-p G = +2 1 10 FREQUENCY (MHz) 100 1000
02916-E-013 02916-E-015
-9 0.1
1
10 FREQUENCY (MHz)
100
1000
-8 0.1
Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42)
8 VOUT = 0.2V p-p 6 G = +2 4 2 VOUT = 4V p-p 0 -2 -4 -6
02916-E-011
Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43)
8 7 RL = 100
VOUT = 2V p-p 6 5 4 3 2 1 0 0.1 VO = 200mV p-p G = +2 1 10 FREQUENCY (MHz) 100 1000
02916-E-014
RL = 1k
GAIN (dB)
-8 0.1
1
10 FREQUENCY (MHz)
100
1000
Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43)
14 VO = 200mV p-p 12 10 8
GAIN (dB)
GAIN (dB)
Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43)
80 120
G = +2 RF = RG = 1k, RS = 500 RF = RG = 500, RS = 250 RF = RG = 500, RS = 250, CF = 2.2pF
60
OPEN-LOOP GAIN (dB)
PHASE 60
PHASE (DEGREES)
40 GAIN 20
0
6 4 2 0 -2 RF = RG = 1k, RS = 500, CF = 3.3pF
-60
0
-120
02916-E-012
-4 0.1
1
10 FREQUENCY (MHz)
100
1000
-20 0.01
0.1
1
10
100
-180 1000
FREQUENCY (MHz)
Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)
Figure 15. Open-Loop Response
Rev. E | Page 9 of 28
AD8065/AD8066
-30 -40 -50 -60
DISTORTION (dBc) DISTORTION (dBc)
-40 G = +2
-50
-60 -70 -80 -90 -100 -110
02916-E-016
HD2 G = +2 -70 HD2 G = +1 -80 HD3 G = +2
HD2 RL = 150 HD2 RL = 1k HD3 RL = 1k HD3 RL = 150
-90 HD3 G = +1 -100
1
10 FREQUENCY (MHz)
100
1
10 FREQUENCY (MHz)
100
Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43)
-30 -40 -50
DISTORTION (dBc)
-20
Figure 19. Harmonic Distortion vs. Frequency for Various Gains (See Figure 42 and Figure 43)
VS = 12V G = +2
G = +2 VS = 12V F = 1MHz
DISTORTION (dBc)
-30 -40 -50 -60
HD2 VO = 20V p-p HD3 VO = 20V p-p
-60 -70 -80 -90 -100 -110 -120 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUTPUT AMPLITUDE (V p-p) HD3 RL = 300 HD2 RL = 150 HD3 RL = 150
HD2 VO = 10V p-p -70 -80 -90 -100 -110 HD2 VO = 2V p-p HD3 VO = 2V p-p 1.0 FREQUENCY (MHz) 10.0
02916-E-020 02916-E-021
HD3 VO = 10V p-p
HD2 RL = 300
Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = 12 V (See Figure 43)
50 RL = 100 45
INTERCEPT POINT (dBm)
02916-E-017
-120 0.1
Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes (See Figure 42 and Figure 43)
100
VS = 12V
40
VS = 5V
NOISE (nV/ Hz)
35
10
30 VS = +5V 25 20
1 FREQUENCY (MHz)
10
02916-E-018
15
1 10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage
Figure 21. Voltage Noise
Rev. E | Page 10 of 28
02916-E-019
-120 0.1
-110 0.1
AD8065/AD8066
G = +1 CL = 5pF G = +1 CL = 20pF
50mV/DIV
20ns/DIV
02916-E-022
50mV/DIV
20ns/DIV
02916-E-025
Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52)
G = +1 VS = 12V VOUT = 10V p-p VOUT = 4V p-p
Figure 25. Small Signal Transient Response 5 V (See Figure 42)
G = +2 5s VS = 12V
VOUT = 10V p-p
VOUT = 2V p-p
VOUT = 2V p-p
2V/DIV
80ns/DIV
02916-E-023
2V/DIV
80ns/DIV
02916-E-026
Figure 23. Large Signal Transient Response (See Figure 42)
G = -1 VS = 5V -IN OUT
Figure 26. Large Signal Transient Response (See Figure 43)
IN OUT G = +1 VS = 5V
1.5V/DIV
100ns/DIV
02916-E-024
1.5V/DIV
100ns/DIV
02916-E-027
Figure 24. Output Overdrive Recovery (See Figure 44)
Figure 27. Input Overdrive Recovery (See Figure 42)
Rev. E | Page 11 of 28
AD8065/AD8066
VIN = 140mV/DIV VIN = 500mV/DIV
+0.1%
VOUT - 2VIN
+0.1%
-0.1%
t=0
-0.1%
t=0 VOUT - 2VIN
2mV/DIV
64s/DIV
02916-E-028
2mV/DIV
10ns/DIV
02916-E-031
Figure 28. Long-Term Settling Time (See Figure 49)
0 42 36 30 24 18 12 6 0 10 -15 +Ib 5 0 -5 -10 -15 -20 -25
02916-E-029
Figure 31. 0.1% Short-Term Settling Time (See Figure 49)
+Ib -Ib
-5
INPUT BIAS CURRENT (pA)
-Ib -10
-25
Ib (pA)
-20
+Ib
25
35
45
55
65
75
85
-8
-6
-4
-2
0
2
4
6
8
10
12
TEMPERATURE (C)
COMMON-MODE VOLTAGE (V)
Figure 29. Input Bias Current vs. Temperature
0.3 40 35 0.2 30
Figure 32. Input Bias Current vs. Common-Mode Voltage Range (see the Input and Output Overload Behavior section)
N = 299 SD = 0.388 MEAN = -0.069
OFFSET VOLTAGE (mV)
0.1 VS = +5V 0 VS = 5V
25 20 15
-0.1
VS = 12V 10
-0.2
5
02916-E-033
02916-E-030
-0.3 -14 -12 -10 -8
-6
-4
-2
0
2
4
6
8
10
12
14
0 -2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (mV)
Figure 30. Input Offset Voltage vs. Common-Mode Voltage
Figure 33. Input Offset Voltage
Rev. E | Page 12 of 28
02916-E-032
-30
-30 -12 -10
FET INPUT STAGE
-Ib
BJT INPUT STAGE
Ib (A)
AD8065/AD8066
-30
100
-40
10
-50
OUTPUT IMPEDANCE ()
CMRR (dB)
-60
1
G = +1
-70
VS = 12V
G = +2 0.1
-80 -90 VS = 5V
0.01
1
10 FREQUENCY (MHz)
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 34. CMRR vs. Frequency (See Figure 46)
0.30
Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)
80
0.25 VCC - VOH 0.20
OUTPUT SATURATION VOLTAGE (mV)
OUTPUT SATURATION VOLTAGE (V)
70 VCC - VOH 60
0.15
50
0.10 VOL - VEE 0.05
VOL - VEE
40
02916-E-035
0
10
20 ILOAD (mA)
30
40
25
35
45
55
65
75
85
TEMPERATURE (C)
Figure 35. Output Saturation Voltage vs. Output Load Current
0 -10 -20 -30 -PSRR +PSRR 0 -10 -20
Figure 38. Output Saturation Voltage vs. Temperature
VIN = 2V p-p G = +1
PSRR (dB)
-40 -50 -60 -70 -80 -90
CROSSTALK (dB)
-30 -40 -50 -60 -70 A TO B -80 B TO A
02916-E-036
0.1
1
10
100
1000
1
10 FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)
Figure 39. Crosstalk vs. Frequency (See Figure 51)
Rev. E | Page 13 of 28
02916-E-039
-100 0.01
-90 0.1
02916-E-038
0
30
02916-E-037
02916-E-034
-100 0.1
0 100
AD8065/AD8066
6.60 VS = 12V 6.55 VS = 5V 115 VS = 12V 125 120
SUPPLY CURRENT (mA)
6.50 6.45 VS = +5V 6.40
OPEN-LOOP GAIN (dB)
110 105 100 95 VS = 5V 90 VS = +5V
6.35
6.30 6.25 -40
85
02916-E-041
02916-E-040
80 0 10 20 ILOAD (mA) 30 40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages
Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages
Rev. E | Page 14 of 28
AD8065/AD8066 TEST CIRCUITS
SOIC-8 Pinout
+VCC 4.7F
+VCC 4.7F
0.1F
0.1F
24.9
499
2.2pF 499
VIN 49.9
RSNUB
FET PROBE
FET PROBE
AD8065
VIN 1k 49.9 0.1F CLOAD
249
AD8065
1k 0.1F
02916-E-042
4.7F
-VEE
-VEE
Figure 42. G = +1
Figure 44. G = -1
+VCC 4.7F
+VCC 4.7F
0.1F 2.2pF 499 499
0.1F 24.9
FET PROBE
AD8065
VIN 49.9 249 0.1F
RSNUB
AD8065
NETWORK ANALYZER S22
1k CLOAD
0.1F
4.7F
02916-E-043
4.7F
02916-E-045
-VEE
-VEE
Figure 43. G = +2
Figure 45. Output Impedance G = +1
Rev. E | Page 15 of 28
02916-E-044
4.7F
AD8065/AD8066
+VCC 4.7F
VIN 1V p-p
+VCC
0.1F
49.9 24.9
499
499
VIN FET PROBE
FET PROBE
AD8065
49.9 499 499 0.1F 1k
AD8065
0.1F 1k
4.7F
02916-E-046
4.7F
02916-E-048
-VEE
-VEE
Figure 46. CMRR
Figure 48. Positive PSRR
+VCC 4.7F
+VCC 4.7F
0.1F
0.1F
499
499
499
2.2pF 499
249
AD8065
NETWORK ANALYZER S22
249 976 TO SCOPE
AD8065
0.1F 49.9
0.1F
VIN 49.9
4.7F
02916-E-047
4.7F
02916-E-049
-VEE
-VEE
Figure 47. Output Impedance G = +2
Figure 49. Settling Time
Rev. E | Page 16 of 28
AD8065/AD8066
+VCC 4.7F
2.2pF
0.1F 24.9
499
499
5V 1.5V 4.7F
0.1F
FET PROBE
AD8065
249
1k 49.9
FET PROBE
AD8065
VIN 1k 49.9
02916-E-052
02916-E-050
VIN 1V p-p
1.5V
1.5V
-VEE
Figure 50. Negative PSRR
Figure 52. Single Supply
24.9
24.9
FET PROBE
AD8066
+5V 4.7F
1k
0.1F
RECEIVE SIDE
AD8066
VIN 0.1F 1k 49.9 4.7F
02916-E-051
-5V DRIVE SIDE
Figure 51. Crosstalk--AD8066
Rev. E | Page 17 of 28
AD8065/AD8066 THEORY OF OPERATION
The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar (XFCB) process, resulting in an outstanding combination of precision and speed. The supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles common-mode signals from below the negative supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. With voltage noise of 7 nV/Hz and -88 dBc distortion for 1 MHz 2 V p-p signals, the AD8065/AD8066 are a great choice for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capability of the AD8065/AD8066 also make them useful in video applications.
NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE
Solving for the transfer function
2 x f crossover (RG + RF ) VO = VI (RF + RG ) s + 2 x f crossover x RG where fcrossover is the frequency where the amplifier's open-loop gain equals 0 db At dc
VO RF + RG = VI RG
Closed-loop -3 dB frequency
f -3dB = f crossover x RG RF + RG
INVERTING CLOSED-LOOP FREQUENCY RESPONSE
-2 x f crossover x RF VO = VI s (RF + RG ) + 2 x f crossover x RG
CLOSED-LOOP FREQUENCY RESPONSE
The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 53. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown.
RF
At dc
VO R =- F VI RG
Closed-loop -3 dB frequency
f -3dB = f crossover x RG RF + RG
RF
RG VI VE
VI
RG VE
A
VO
A
VO
80
A = (2 x fcrossover)/s
OPEN-LOOP GAIN (A) (dB)
60
40
20
fcrossover = 65MHz
0 0.01 0.1 1 FREQUENCY (MHz) 10 100
Figure 53. Open-Loop Gain vs. Frequency and Basic Connections
Rev. E | Page 18 of 28
02916-E-053
AD8065/AD8066
The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG )/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 will be higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp.
RF
For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance. Actual distortion performance depends on a number of variables:
* * * * *
RG
+VOS - VO
VI
RS
Ib-
A
The closed-loop gain of the application Whether it is inverting or noninverting Amplifier loading Signal frequency and amplitude Board layout
Ib+
02916-E-054
Figure 54. Voltage Feedback Amplifier DC Errors
Figure 54 shows a voltage feedback amplifier's dc errors. For both inverting and noninverting configurations
R + RF R + RF VO (error ) = I b+ x RS G - I x RF + VOS G RG b- RG
Also see Figure 16 to Figure 20. The lowest distortion will be obtained with the AD8065 used in low gain inverting applications, since this eliminates common-mode effects. Higher closed-loop gains result in worse distortion performance.
INPUT PROTECTION
The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation. Excessive power dissipation through the protection devices will destroy or degrade the performance of the amplifier. Differential voltages greater than 0.7 V will result in an input current of approximately (|V+ - V-| 0.7 V)/RI, where RI is the resistance in series with the inputs. For input voltages beyond the positive supply, the input current will be approximately (VI - VCC - 0.7)/RI. Beyond the negative supply, the input current will be about (VI - VEE + 0.7)/RI. If the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 V or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (RI) as shown in Figure 55.
RI > (| V+- V- | - 0.7V) 30mA RI > RI > (VI - VEE - 0.7V) 30mA (VI - VEE + 0.7V) 30mA FOR VI BEYOND SUPPLY VOLTAGES
02916-E-055
The voltage error due to Ib+ and Ib- is minimized if RS = RF || RG (though with the AD8065 input currents at less than 20 pA over temperature, this is likely not a concern). To include commonmode and power supply rejection effects, total VOS can be modeled as
VOS = VOS nom +
VS VCM + PSR CMR
VOS nom is the offset voltage specified at nominal conditions, VS is the change in power supply from nominal conditions, PSR is the power supply rejection, VCM is the change in common-mode voltage from nominal conditions, and CMR is the common-mode rejection.
WIDEBAND OPERATION
Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of +1, +2, and -1. Source impedance at the summing junction (RF || RG) will form a pole in the amplifier's loop response with the amplifier's input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 to 1 k are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (CF) in parallel with the feedback resistor, as illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier.
FOR LARGE | V+ - V- | RI
AD8065
VI
VO
Figure 55. Current Limiting Resistor
Rev. E | Page 19 of 28
AD8065/AD8066
THERMAL CONSIDERATIONS
With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT-23-5 (thermal resistance of 160C/W). VOS temperature drift is trimmed to guarantee a maximum drift of 17 V/C, so it can change up to 0.425 mV due to warm-up effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V. Ib increases by a factor of 1.7 for every 10C rise in temperature. Ib will be close to 5 times higher at 24 V supplies as opposed to a single 5 V supply. Heavy loads will increase power dissipation and raise the chip junction temperature as described in the Maximum Power Dissipation section. Care should be taken to not exceed the rated power dissipation of the package. The circuit is arranged such that when the input commonmode voltage exceeds a certain threshold, the input JFET pair's bias current will turn OFF, and the bias current of an auxiliary NPN pair will turn ON, taking over control of the amplifier. When the input common-mode voltage returns to a viable operating value, the FET stage turns back ON, the NPN stage turns OFF, and normal operation resumes. The NPN pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. For operation beyond the FET stage's common-mode limit, the amplifier's VOS will change to the NPN pair's offset (mean of 160 V, standard deviation of 820 V), and Ib will increase to the NPN pair's base current up to 45 A (see Figure 32). Switchback, or recovery time, is about 100 ns, see Figure 27. The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a 5 V supply is shown in Figure 24.
INPUT AND OUTPUT OVERLOAD BEHAVIOR
The AD8065/AD8066 have internal circuitry to guard against phase reversal due to overdriving the input stage. A simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in Figure 56.
Rev. E | Page 20 of 28
AD8065/AD8066 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 F (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 F tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board, at the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and therefore the high frequency impedance of the path. High speed currents in an inductive ground return will create an unwanted voltage noise.
VCC R1 R5 TO REST OF AMP Q2 Q5
VTHRESHOLD
VBIAS D1 R3 Q1 VN D3 Q3 S R4 D2 Q4 R7 S Q6 D4 VP R6
R2
R8
Q7
-VEE
Figure 56. Simplified Input Stage
Rev. E | Page 21 of 28
02916-E-056
IT1
IT2
AD8065/AD8066
The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier's gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board.
LEAKAGE CURRENTS
Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs will set up leakage currents through the PC board insulator, for example, 1 V/100 G = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To significantly reduce leakage, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. Also, low absorption materials, such as Teflon(R) or ceramic, could be necessary in some instances.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect.
*
As shown in Figure 57, put a small value resistor (RS) in series with the output to isolate the load capacitor from the amp's output stage. A good value to choose is 20 (see Figure 10). Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from -IN to the output.
*
AD8065
VI
RS = 20 CL
VO
02916-E-057
Figure 57. Output Isolation Resistor
CF
RF
IPHOTO CS
RSH = 1011 CD
CM
CM VB RF
VO
Figure 58. Wideband Photodiode Preamp
Rev. E | Page 22 of 28
02916-E-058
CF + CS
AD8065/AD8066
INPUT-TO-OUTPUT COUPLING
In order to minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs.
The preamp's output noise over frequency is shown in Figure 59.
1 2 RF (CF + CS + CM + 2CD) 1 2RFCF
f1 =
WIDEBAND PHOTODIODE PREAMP
Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is where
VOUT = I PHOTO x RF 1 + sC F RF
VOLTAGE NOISE (nV/ Hz)
f2 = f3 =
fCR
(CS + CM + 2CD + CF) /CF
RF NOISE
where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF set the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier's summing junction, including CS and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier's loop transmission that can result in peaking and instability. Adding CF creates a 0 in the loop transmission, which compensates for the pole's effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45 phase margin (f(45)) is defined by the expression
f2 f1
VEN (CF + CS + CM + 2CD)/CF
f3
NOISE DUE TO AMPLIFIER
FREQUENCY (Hz)
Figure 59. Photodiode Voltage Noise Contributions
f ( 45 ) =
f CR 2 x RF x C S
The pole in the loop transmission translates to a 0 in the amplifier's noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission 0 introduced by CF limits the amplification. The noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which will add to the output noise. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 k, CS = 15 pF, and CF = 2 pF (bandwidth of about 1.6 MHz) are also listed.
where fCR is the amplifier crossover frequency, RF is the feedback resistor, and CS is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). The value of CF that produces f(45) can be shown to be CF = CS 2 x RF x f CR
The frequency response in this case will show about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half will result in a flat frequency response, with about 5% transient overshoot.
Table 5. RMS Noise Contributions of Photodiode Preamp
Contributor RF (x2) Amp to f1 Amp (f2 - f1) Expression RMS Noise with RF = 50 k, CS = 15 pF, CS = 15 pF 64.5 V 2.4 V
2 x 4 kT x RF x f 2 x 1.57 VEN x VEN x VEN x f1 C S + C M + C F + 2C D x CF C S + C M + C D + 2C F x CF f 2 - f1 f 3 x 1.57
31 V
Amp to (past f2)
260 V
270 V (Total)
Rev. E | Page 23 of 28
02916-E-059
VEN
AD8065/AD8066
VCC
0.1F RS1 VN 1/2
4.7F
AD8066
4.7F
2.2pF
0.1F VEE
R2 500 VCC 4.7F
R1 500 RF = 500
0.1F
AD8065
4.7 F
VO
RG 0.1 F R3 RF = 500 VCC 500 VEE
0.1 F
4.7F R4 500
1/2 RS2 VP
2.2pF
AD8066
4.7F
VEE
Figure 60. High Speed Instrumentation Amplifier
HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER
Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065/AD8066. The dc transfer function is VOUT
1 + 1000 = (VN - VP ) RG
RF || 0.5(RG). This is the value to be used for matching purposes.
VIDEO BUFFER
The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 61. The G = +2 configuration compensates for the voltage division of the signal due to the signal termination. This buffer maintains 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (Figure 7). Differential gain and phase have been measured to be 0.02% and 0.028 at 5 V supplies.
+VS
For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 for 50 source impedance). The bandwidth for G = +1 will be 50 MHz. For higher gains, the bandwidth will be set by the preamp, equaling Inamp-3dB = ( f CR x RG )/ (2 x RF ) Common-mode rejection of the inamp will be primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated
249 + VI -
0.1 F
4.7 F 75
AD8065 75 0.1 F -VS 2.2pF 4.7 F + VO -
499
The summing junction impedance for the preamps is equal to
Figure 61. Video Buffer
Rev. E | Page 24 of 28
02916-E-061
(1 - 2 ) VO = VCM (1 + 1) 2
499
02916-E-060
0.1 F
AD8065/AD8066 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
8
3.00 BSC
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
5
3.00 BSC
4
4.90 BSC
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
0.15 0.00 0.38 0.22 COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 62. 8-Lead Standard Small Outline Package Narrow Body [SOIC] (R-8) Dimensions shown in millimeters (inches)
Figure 64. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
2.90 BSC
5
4
1.60 BSC
1
2.80 BSC
2 3
PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC
1.45 MAX
0.22 0.08 10 5 0 0.60 0.45 0.30
0.15 MAX
0.50 0.30
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 63. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5) Dimensions shown in millimeters
Rev. E | Page 25 of 28
AD8065/AD8066
ORDERING GUIDE
Model AD8065AR AD8065AR-REEL AD8065AR-REEL7 AD8065ART-REEL AD8065ART-R2 AD8065ART-REEL7 AD8066AR AD8066AR-REEL AD8066AR-REEL7 AD8066ARZ1 AD8066ARZ-REEL1 AD8066ARZ-REEL71 AD8066ARM AD8066ARM-REEL AD8066ARM-REEL7 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Outline R-8 R-8 R-8 RT-5 RT-5 RT-5 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 Branding
HRA HRA HRA
HIB HIB HIB
1
Z = Pb-free part.
Rev. E | Page 26 of 28
AD8065/AD8066 NOTES
Rev. E | Page 27 of 28
AD8065/AD8066 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02916-0-2/04(E)
Rev. E | Page 28 of 28

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